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fn8657 rev 3.00 page 1 of 34 december 12, 2014 fn8657 rev 3.00 december 12, 2014 ISL78268 55v synchronous buck controller with integrated 3a driver datasheet the ISL78268 is a grade 1, automotive, synchronous buck controller with integrated high/low side mosfet drivers. it supports a wide operating input voltage range of 5v to 55v and up to 60v at v in when not switching. the integrated driver offers adaptive dead-time control and is capable of supplying up to 2a sourcing and 3a si nking current, allowing the ISL78268 to support power stages designed for a wide range of loads, from under 1a to over 25a. ISL78268?s fully synchronous architecture enables power conversion with very high efficiency and improved thermal performance over standard buck converters. the ISL78268 also offers diode emulation mode for improved light load efficiency. while ISL78268 is a peak curr ent mode pwm controller, it also includes a dedicated average output current modulation loop, which achieves constant output current limiting for applications such as battery ch arging, super-cap charging, and temperature control systems where a constant current must be provided. the ISL78268 supports switchin g frequencies from 50khz to 1.1mhz allowing the user the flexibility to trade-off switching frequency and efficiency against the size of external components. the ISL78268 offers comprehensive protection features. it includes robust current protecti on with cycle-by-cycle peak current limiting, average current limiting, and a selectable hiccup or latch-off fault respon ses. in addition, it offers protection against over-temperature, as well as input and output overvoltages. features ? wide input range 5v to 55v (switching); withstand 60v (non-switching) ? integrated 2a sourcing, 3a sinking mosfet drivers ? constant current regulation/limiting - dedicated average current control loop ? adjustable switching frequency or external synchronization from 50khz up to 1.1mhz ? low shutdown current, i q <1 a ? peak current mode control with adjustable slope compensation ? selectable diode emulation mode for high efficiency at light load ? input and output ovp, cycle-by-cycle current limiting, average current ocp, otp ? selectable hiccup or latch-off fault responses ? pb-free 24 ld 4x4 qfn package (rohs compliant) ? aec-q100 qualified applications ? automotive power ? telecom and industrial power supplies ? general purpose power ?supercap charging related literature ? an1946 , ?ISL78268eval1z evaluation board user guide? figure 1. simplified typical application schematic f igure 2. efficiency curves (ISL78268eval1z/de mode) ISL78268 vcc boot ph fb comp vin lg clkout pgood ug pgnd ss pvcc slope fsync en vin en_ic isen1p isen1n pll_comp pvcc isen2p isen2n hic/latch sgnd imon/de vcc power good pvcc vout 50 55 60 65 70 75 80 85 90 95 100 012345 i out (a) v out = 12v, t a = +25c v in = 15v v in = 24v v in = 36v v in = 55v efficiency (%)
ISL78268 fn8657 rev 3.00 page 2 of 34 december 12, 2014 table of contents related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical application schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 operation description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 synchronous buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 adaptive dead-time control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 operation initialization and soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 clock generator and synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 bootstrap for high-side nmos drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 pwm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 adjustable slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 light load efficiency enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 average constant current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 fault monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 internal 5.2v ldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 output voltage setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 output inductor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 input capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 power mosfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 bootstrap capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 loop compensation design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 vcc input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 current sense circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 layout consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ISL78268 fn8657 rev 3.00 page 3 of 34 december 12, 2014 pin configuration ISL78268 (24 ld 4x4 qfn) top view functional pin description pin name pin # description slope 1 this pin programs the slope of the internal slope compensation. a resistor should be connected from the slope pin to gnd. pleas e refer to ? adjustable slope compensation ? on page 24 for how to choose this resistor value. fb 2 the inverting input of the transconductance amplifier. a resist or divider must be placed between the fb pin and the output r ail to set the output voltage. comp 3 the output of the transconductance amplifier. place the compensation network between the comp pin and gnd for compensation loop design. ss 4 use this pin to set up the desired soft-start time. a capacito r placed from ss to gnd will set up the soft-start ramp rate a nd in turn determine the soft-start time. imon/de 5 imon/de is a bifunctional pin as either th e average current monitor/protection or swit ching mode selection (diode emulation (de ) mode or forced pwm mode). 1. if imon/de pin is connected to vcc (higher than vcc - 0.7v), the device operates in forced pwm mode and the average current monitoring/limiting feature is disabled. 2. if a resistor (and a filter capacitor in parallel) is connecte d between imon/de and gnd, the device operates in de mode and the average current monitoring/limiting feature is enabled. a current which is proportional to the current sensed at i sen2 is sourced from the imon/de pin. with an r/c network at the imon/de pin to gnd, the voltage at imon/de pin describes average output current. when average current monitoring/limiting feature is enabled and de mode is selected; 1. if imon/de is higher than 2v, the device enters average current protection mode with the hiccup/latch-off as the fault respon se. 2. if imon/de reaches to 1.6v, the device ente rs the average constant current control loop. 3. if the imon/de pin voltage is lower than 1.6v (typ), the device operates as a normal buck regulator in de mode. pgood 6 provides an open-drain power-good signal. when the output voltage is within +15/ -12% of the nominal output regulation poi nt and soft-start is completed, the internal pgood open-drain transistor is open. it will be pulled low once output uv/ov or input ov conditions are detected. requires pull-up resistor connecting to vcc. fsync 7 the oscillator switching frequency is adjusted with a resistor from this pin to gnd. the internal oscillator locks to the rising edge of a square pulse waveform if this pin is driven by an external clock. there is a 325ns delay from the fsync pin?s input clock ris ing edge to ug rising edge. sgnd 8 signal ground pin; the reference of internal analog circuits. connect this pin to a large quiet copper ground plane. in pc b layout planning, avoid having switching current flowing into the sgnd ar ea (including the ic pad that is connected to the quiet large copper ground plane also). 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 epad lg ph pgnd pvcc ug comp imon/de slope fb ss pgood f s y n c boot s g n d pll_comp e n c l k o u t h i c / l a t c h v c c i s e n 2 p i s e n 1 p i s e n 2 n vin isen1n
ISL78268 fn8657 rev 3.00 page 4 of 34 december 12, 2014 en 9 this pin is a threshold-sensitive enable input for the controller. connecting the power supply input to the en pin through a n appropriate resistor divider prov ides a means to have input voltage uvlo. when en pin is driven above 1.2v, the ISL78268 is act ive depending on status of the internal por, and pending fault stat es. driving the en pin below 1.1v will clear all fault states an d the ISL78268 will soft-start when reenabled. pll_comp 10 this pin serves as the compensation node for the pll. a second order passive loop filter connected between the pll_co mp pin and gnd compensates the pll feedback loop. hic/latch 11 this pin is used to select either hiccup or latcho ff response for faults including output overvoltage, v in overvoltage, peak overcurrent protection (oc2) and average overcurrent protection. hic/latch = high to activate hiccup fault response, hic/latch = low to have latchoff fault response. either toggling en pin or recycling vcc por can reset the ic from latchoff status. clkout 12 this pin provides a clock signal to sync hronize with another ISL78268. the rising edge signal on the clkout pin is delayed 18 0 from the rising edge of ug to facilitate 2-ph ase interleaved operation using two ics. pgnd 13 this power gnd pin provides the return path for the low-side mo sfet drive. note this pin carries the noisy driving current and the trace connected to the low-side mosfet and pvcc decoupling capaci tors should be as short as possible. any sensitive analog sign al trace should not share common traces with th is driving return path. connect this pin directly to the ground copper plane and pu t several vias as close as possible to this pin. pvcc 14 output of the internal linear regulator that provides bias for both high-side and low-side drives. the pvcc operating range is 4.75v to 5.5v. a minimum 4.7f ceramic capacitor should be used between pvcc and pgnd for noise decoupling purpose. this capacitor provides a noisy driving current and its ground pad should have several vias connecting to the ground copper plane. lg 15 the low-side mosfet gate drive output. ph 16 phase node. connect this pin to the source of the high-side mosfets and the drain of th e low-side mosfets. this pin represents the return path for the high-side gate drive. ug 17 high-side mosfet gate drive output. boot 18 this pin provides bias voltage to the high -side mosfet driver. a bootstrap circuit is used to create a voltage suitable to driv e the external n-channel mosfet. place a 1f ceramic capacitor between the bo ot and ph pins, and a switching diode from pvcc to boot. vin 19 connect input rail to this pin. this pin is connected to the input of the internal linear regulator, generating the power necessary to operate the chip. it is recommended the dc voltage applied to the vin pin does not exc eed 55v when the ic is switching. vin can stand up to 60v when ic is not switching. isen1n 20 the isen1n pin is a negative potential input pin of the first cu rrent sense amplifier (csa1). this amplifier senses the signal on the current-sense resistor placed in series with the high-side mosf et. the sensed current information is used for peak current mode control and overcurrent protection. isen1p 21 the isen1p pin is a positive potential input pin of the first current sense amplifier (csa1). isen2n 22 the isen2n pin is a negative potential input pin of the second current sense amplifier (csa2). this amplifier senses the contin uous output inductor current either by dcr sensin g method or using a sense resistor in seri es with the inductor for more accurate se nsing. the sensed current signal is used for 3 functions: - accurately limiting the average output cu rrent for constant output current control - achieve diode emulation - achieve average ocp (comparator at imon/de pin with 2v reference) isen2p 23 the isen2p pin is a positive potential inpu t pin of the second current-sense amplifier (csa2). vcc 24 this pin provides bias power for the ic analog circuitry. an rc filter is recommended between this pin and the bias supply (ran ge of 4.75v to 5.5v, typically from pvcc). a minimum 1f ceramic capacitor should be used between vcc and gnd for noise decoupling purposes. epad bottom thermal pad. it is not connected to any electrical potential of the ic. in layo ut it must be connected to a pcb large gr ound copper plane that doesn?t contain noisy power flows. put multiple vias (as many as possible) in this pad connecting to the ground copp er plane to help reduce the ic?s ? ja . functional pin description (continued) pin name pin # description
ISL78268 fn8657 rev 3.00 page 5 of 34 december 12, 2014 ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL78268arz 782 68arz -40 to +125 24 ld 4x4 qfn l24.4x4h ISL78268eval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL78268 . for more information on msl please see techbrief tb363 .
fn8657 rev 3.00 page 6 of 34 december 12, 2014 ISL78268 block diagram 5.2v ldo vin pvcc vcc 1.2v en ss 1.15vref 0.87vref fb vo_uv pgood gm vref = 1.6v fb comp vco clkout pll_comp fsync slope s q r2 r1 isen1p isen1n boot ug ph lg oc1 i sen1 2v oc_avg 70a oc1 i sen1_oc2 sgnd 5a fault vo_ov pvcc pgnd hiccup/ latchoff en_sw pgnd csa2 isen2p isen2n i sen2_zcd i sen2 zero cross detection + gm pwm control vin/30 vref_vinov vin_ov 1/30 93a oc2 sgnd clock clock sgnd oc_avg en_ss initialization delay pll over temp ss_done 1.6v por imon/de hic/latch slope compensation (i sen2 +68a)/8 i sen1_oc1 i slope 3.4v epad n.c. -50a negative oc i sen2_neg csa1 112a 112a a v = 1 112a 112a a v = 1 vcc - 0.7v soft-start logic + + - + - + - + - + - + - + - -
ISL78268 fn8657 rev 3.00 page 7 of 34 december 12, 2014 typical application schematics figure 3. synchronous buck with constant average i out hic/latch : connect to either v cc for latch-off mode or gnd for hiccup mode ISL78268 vcc boot ph fb comp vin lg clkout pgood ug pgnd ss pvcc slope fsync en vin en_ic isen1p isen1n pll_comp pvcc isen2p isen2n hic/latch sgnd imon/de vcc power good pvcc vout vcc r fsync c pvcc r pllcmp c pllcmp1 c pllcmp2 r slope r cmp c cmp c ss c vcc r imon c imon r svcc c in r set1b r set1a r bias1b r bias1a r sen2 r sen1 c isen1 c boot l r set2b r set2a r bias2b r bias2a c isen2 c out r fb1 r fb0 r pg q 1 q 2 d bt hic/latch: connect to either v cc for hiccup mode or gnd for latch-off mode
ISL78268 fn8657 rev 3.00 page 8 of 34 december 12, 2014 figure 4. synchronous buck (forced pwm) typical application schematics (continued) imon/de : connect to v cc for forced pwm mode hic/latch : connect to either v cc for latch-off mode or gnd for hiccup mode ISL78268 vcc boot ph fb comp vin lg clkout pgood ug pgnd ss pvcc slope fsync en vin en_ic isen1p isen1n pll_comp pvcc isen2p isen2n hic/latch sgnd imon/de vcc power-good pvcc vout vcc r fsync c pvcc r pllcmp c pllcmp1 c pllcmp2 r slope r cmp c cmp c ss c vcc r svcc c in r set1b r set1a r bias1b r bias1a r sen2 r sen1 c isen1 c boot l r set2b r set2a r bias2b r bias2a c isen2 c out r fb1 r fb0 r pg q 1 q 2 d bt vcc hic/latch: connect to either v cc for hiccup mode or gnd for latch-off mode
ISL78268 fn8657 rev 3.00 page 9 of 34 december 12, 2014 figure 5. synchronous buck with dcr sensing typical application schematics (continued) imon/de : connect to v cc for forced pwm mode hic/latch : connect to either v cc for latch-off mode or gnd for hiccup mode ISL78268 vcc boot ph fb comp vin lg clkout pgood ug pgnd ss pvcc slope fsync en vin en_ic isen1p isen1n pll_comp pvcc isen2p isen2n hic/latch sgnd imon/de vcc power-good pvcc vout vcc r fsync c pvcc r pllcmp c pllcmp1 c pllcmp2 r slope r cmp c cmp c ss c vcc r svcc c in r set1b r set1a r bias1b r bias1a r dcrs r sen1 c isen1 c boot l r set2 r bias2 c out r fb1 r fb0 r pg q 1 q 2 d bt vcc c dcrs hic/latch: connect to either v cc for hiccup mode or gnd for latch-off mode
ISL78268 fn8657 rev 3.00 page 10 of 34 december 12, 2014 p absolute maximum rating s thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +60v ph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +60v boot, ug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +65v upper driver supply voltage, v boot - v ph . . . . . . . . . . . . . . - 0.3v to +6.5v pvcc, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +6.5v v isenxp - v isenxp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6v isen1p, isen1n, isen2p, isen2n . . . . . . . . . . . . . . . . . . . . . - 0.3v to +60v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to vcc + 0.3v esd rating human body model (tested per aec-q100-002) . . . . . . . . . . . . . . . . 2kv machine model (tested per aec-q100-003) . . . . . . . . . . . . . . . . . . . 200v charged device model (tested per aec-q100-011). . . . . . . . . . . . . 750v latchup rating (tested per aec-q100-004) . . . . . . . . . . . . . . . . . . . 100ma thermal resistance ? ja (c/w) ? jc (c/w) 24 ld 4x4 qfn package ( notes 4 , 5 ) . . . . . . . . . 39 3.5 maximum junction temperature (plastic package) . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v to 55v ph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 55v pvcc, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75v to 5.5v upper driver supply voltage, v boot - v ph . . . . . . . . . . . . . . . . . . 3.5v to 6v isen1p, isen1n, isen2p, isen2n commo n mode voltage . . . . 4v to 55v isen1p to isen1n and isen2p to isen 2n differential voltage . . . . 0.3v operational ambient temperature range (automotive). . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. unless otherwise noted, all voltages specif ied in this specification are refer to gnd. electrical specifications refer to the block diagram ( page 6 ) and typical application schematics ( page 7 ). operating conditions unless otherwise noted: v in = 12v, v pvcc = 5.2v and v vcc = 5.2v, en = 5.0v, t a = -40c to +125c. typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. parameter symbol test conditions min ( note 7 )typ max ( note 7 )units supply input input voltage range vin for v in = 5v, the internal ldo dropout (v in - pvcc) <0.25v 555 v input supply current (enabled mode) to vin pin i q_sw r fsync = 40.2k (f sw = 300khz), lg = open, ug = open 5 7 ma i q_non-sw fsync = 5v, lg = open, ug = open 2.7 3.5 ma input supply current (shutdown mode) to vin pin i q_sd_vin en = gnd, v in = 12v 0.15 0.5 a en = gnd, v in = 55v 0.2 1 a input leakage current (shutdown mode) to each of isen1p/isen1 n/isen2p/isen2n pins i q_sd_isenxp/n en = gnd, isen1p (or isen1n/isen2p/isen2n) = 55v, v in = 55v -1 0 1 a input overvoltage protection v in switching-disabled threshold en = 5v, v in rising 56 57.5 59.5 v v in overvoltage recovery threshold 52.5 54.5 57 v v in switching-disabled threshold hysteresis 3v v in overvoltage hiccup retry delay from the time fault is removed to initiation of soft-start 500 ms internal linear regulator ldo output voltage (pvcc pin) v pvcc v in = 6v to 55v, c pvcc = 4.7f from pvcc to pgnd, i pvcc = 10ma 5 5.2 5.4 v ldo dropout voltage (pvcc pin) v dropout v in = 4.9v, c pvcc = 4.7f from pvcc to pgnd, i vcc = 80ma 0.3 v ldo current foldback limit (pvcc pin) i oc_ldo v in = 6v, c pvcc = 4.7f from pvcc to pgnd v pvcc = 2.5v 150 230 280 ma ldo output short current (pvcc pin) i ocfb_ldo v in = 6v, c pvcc = 4.7f from pvcc to pgnd v pvcc = 0v 100 150 220 ma
ISL78268 fn8657 rev 3.00 page 11 of 34 december 12, 2014 power-on reset (for both pvcc and vcc) rising v pvcc/vcc por threshold v porh_rise 4.35 4.55 4.75 v falling v pvcc/vcc por threshold v porl_fall 4.1 4.15 4.3 v v pvcc/vcc por hysteresis v porl_hys 0.4 v phase lock loop locking time t pll_dly from por to initiation of soft-start. r pllcmp = 3.24k, c pllcmp1 = 6.8nf, c pllcmp2 =1nf, r fsync = 40.2k, f sw = 300khz 0.8 ms en enable threshold v enh rising 1.1 1.2 1.3 v v enl falling 1.04 1.14 1.24 v v en_hys hysteresis 60 mv input resistance en = 4v 3000 5000 8000 k en = 6v 5 k oscillator pwm switching frequency f osc r fsync = 249k (0.1%) 47.5 50 52.5 khz r fsync = 40.2k (0.1%) 285 300 315 khz r fsync = 10k (0.1%) 1036 1100 1155 khz switching frequency range t a = +25c, v in = 12v 50 1100 khz synchronization range at fsync t a = +25c, v in = 12v 50 1100 khz clkout high level clkout output voltage clkout h i clkout = 500a vcc-0.4 vcc-0.1 v low level clkout output voltage clkout l i clkout = -500a 0.1 0.4 v output pulse width c clkout = 100pf 270 ns phase shift from ug rising edge to clkout pulse rising edge ug = open, c clkout = open 180 synchronization (fsync pin) input high threshold vih 3.5 v input low threshold vil 1.5 v input pulse width - rise_to_fall 20 20,000 ns input pulse width - fall_to_rise 20 20,000 ns delay from input pulse rising to ug rising edge ug = open 325 ns soft-start soft-start current i ss v ss = 0v 4.5 5 5.5 a soft-start pin prebias voltage range v ss_pre in prebias output condition; v ss_pre = v fb 01.6 v soft-start prebias voltage accuracy v fb = 500mv -25 25 mv soft-start clamp voltage v ssclamp 3 3.4 3.8 v reference voltage reference accuracy measured at fb pin 1.584 1.6 1.616 v fb pin input bias current v fb = 1.6v -0.05 0.05 a error amplifier transconductance gain 2ms comp output impedance 10 m unity gain bandwidth c cmp = 100pf from comp pin to gnd 11 mhz electrical specifications refer to the block diagram ( page 6 ) and typical application schematics ( page 7 ). operating conditions unless otherwise noted: v in = 12v, v pvcc = 5.2v and v vcc = 5.2v, en = 5.0v, t a = -40c to +125c. typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units
ISL78268 fn8657 rev 3.00 page 12 of 34 december 12, 2014 slew rate c cmp = 100pf from comp pin to gnd 2.5 v/s comp output current capability 300 a comp output voltage high 3.5 3.7 3.9 v comp output voltage low 0.3 v slope compensation setting slope pin voltage 500 mv slope accuracy r slope = 20k (0.1%) -30 30 % r slope = 40.2k (0.1%) -30 30 % current sense amplifier isenxn, isenxp common mode voltage range 455 v isenxn, isenxp bias current i senxbias sinking into pin, en = 5v, v isenxn = v isenxp = 4v to 55v 90 112 130 a zero crossing detection zero crossing detection (zcd) threshold v zcd_th r sen differential voltage r set2a +r set2b = 665 (0.1%) r bias2a +r bias2b = 665 (0.1%) see page 7 for r set resistors 1.3 mv overcurrent protection peak current cycle-by-cycle limit voltage threshold v oc1 r sen differential voltage r set1a +r set1b = 665 (0.1%) r bias2a +r bias2b = 665 (0.1%) see page 7 for r set resistors 32 47 60 mv peak current cycle-by-cycle limit delay ug = open, from v oc1 threshold to ug falling 50 ns peak current hiccup/latch-off voltage threshold v oc2 r sen differential voltage r set1a +r set1b = 665 (0.1%) r bias2a +r bias2b = 665 (0.1%) see page 7 for r set resistors 45 62 75 mv oc2 hiccup/latch-off blanking time consecutive oc2 switching cycles 3 cycles oc2 hiccup retry delay 500 ms average overcurrent protection and constant current limiting loop imon offset current v rsen-csa2 = 0mv, v isen2n = 4v to 55v, r set2a +r set2b = 665 (0.1%) r bias2a +r bias2b = 665 (0.1%) 7.0 8.5 10.0 a imon current accuracy imon csa2 v rsen-csa2 = 25mv, v isen2n = 4v to 55v, r set2a +r set2b = 665 (0.1%) r bias2a +r bias2b = 665 (0.1%) 12 13.2 15 a imon csa2 v rsen-csa2 = 76mv, v isen2n = 4v to 55v, r set2a +r set2b = 665 (0.1%) r bias2a +r bias2b = 665 (0.1%) 21 22.8 26 a fault threshold at imon/de pin s elected latchoff/hiccup response 1.9 2.0 2.1 v oc_avg hiccup retry delay 500 ms constant current limit reference accuracy vref cc 1.584 1.6 1.616 v pwm controller minimum ugate on time t minon_ug ugate pulse width, ug = open, lg = open 240 300 360 ns minimum ugate off time t minoff_ug v comp = 3.5v, ug = open, lg = open 285 ns minimum lgate on time t minon_lg v comp = 3.5v, ug = open, lg = open 140 175 210 ns electrical specifications refer to the block diagram ( page 6 ) and typical application schematics ( page 7 ). operating conditions unless otherwise noted: v in = 12v, v pvcc = 5.2v and v vcc = 5.2v, en = 5.0v, t a = -40c to +125c. typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units
ISL78268 fn8657 rev 3.00 page 13 of 34 december 12, 2014 gate drivers ug source resistance r ugsrc 50ma source current; v boot - v ph = 4.5v 1.2 ug source current i ugsrc ug - ph = 2.5v; v boot - v ph = 4.5v 2.0 a ug sink resistance r ugpd 100ma sink current; v boot - v ph = 4.5v 0.65 ug sink current i ugpd ug - ph = 2.5v; v boot - v ph = 4.5v 3.0 a lg source resistance r lgsrc 50ma source current 1.0 lg source current i lgsrc lg - pgnd = 2.5v 2.0 a lg sink resistance r lgpd 100ma sink current 0.55 lg sink current i lgpd lg - pgnd = 2.5v 3.0 a ug to ph pull-down resistance 50 k lg to pgnd pull-down resistance 50 k boot-ph refreshing detection threshold 3.1 3.3 3.5 v boot-ph refreshing detection threshold hysteresis 100 150 250 mv dead-time delay - ug falling to lg rising t dt1 ug = open, lg = open 45 55 65 ns dead-time delay - lg falling to ug rising t dt2 ug = open, lg = open 45 55 65 ns output overvoltage detection/protection (note: fb_ovp response is selectable to be latchoff or hiccup) fb overvoltage rising trip threshold v fbov_ref percentage of reference point, vfb = 1.6v selected latchoff/hiccup response. 111 115 118 % fb overvoltage recovery threshold 108 112 115 % overvoltage threshold hysteresis 3% fb overvoltage protection delay overvoltage detection filter 1 s fb_ov hiccup retry delay 500 ms output undervoltage detection fb undervoltage falling threshold v fbuv_ref percentage of reference point, vfb = 1.6v 85 87.5 90 % fb undervoltage recovery threshold 88 90.5 93 % undervoltage hysteresis 3% power-good monitor (output overvoltage, output undervoltage, vin overvoltage) pgood leakage current pgood high, v pgood = 5v 1 a pgood low voltage pgood low, i pgood = 0.5ma 0.20 0.4 v pgood rising delay -1 from v ss = 0.95*vref to v ss = v ssclamp , c ss = 15nf 5.6 ms pgood rising delay -2 from v ss = v ssclamp to pgood high 0.5 ms pgood falling delay blanking filter time before transition 10 us hic/latch pin hic/latch input pull-down current v hic/latch = 5v 0.8 1 2 a hic/latch input high threshold 2 v hic/latch input low threshold 0.8 v over-temperature protection over-temperature threshold 160 c over-temperature recovery threshold 145 c note: 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications refer to the block diagram ( page 6 ) and typical application schematics ( page 7 ). operating conditions unless otherwise noted: v in = 12v, v pvcc = 5.2v and v vcc = 5.2v, en = 5.0v, t a = -40c to +125c. typicals are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units
ISL78268 fn8657 rev 3.00 page 14 of 34 december 12, 2014 typical performance all the performance curves are taken from the evalua tion board (ISL78268eval1z) unless otherwise noted. figure 6. frequency se tting (at +25c), v in = 36v figure 7. efficiency (at +25c): de mode, v out = 12v, l = 4.7h, f sw = 300k ? figure 8. efficiency (at +125c): de mode, v out = 12v, l = 4.7h, f sw = 300k ? figure 9. efficiency (at -40c), de mode, v out = 12v, l = 4.7h, f sw = 300k ? figure 10. de mode: v in = 36v, v out = 12v, i out = 2.5a, l = 4.7h, c out = 98f, f sw = 300khz (continuous conduction operation) figure 11. de mode: v in = 36v, v out = 12v, i out = 1.0a, l = 4.7h, c out = 98f, f sw = 300khz (discontinuous conduction operation) 0 200 400 600 800 1000 1200 1400 0 50 100 150 200 250 300 f sw (khz) r fsync (k) 50 55 60 65 70 75 80 85 90 95 100 012345 i out (a) v out = 12v, t a = +25c v in = 15v v in = 24v v in = 36v v in = 55v efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 012345 efficiency (%) i out (a) v in = 15v v in = 25v v in = 36v v in = 55v 50 55 60 65 70 75 80 85 90 95 100 0 12345 efficiency (%) i out (a) v in = 15v v in = 25v v in = 36v v in = 55v 2s/div i l : 2a/div ph: 10v/div v out : 2v/div v in : 5v/div 2s/div i l : 2a/div ph: 10v/div v out : 2v/div v in : 5v/div
ISL78268 fn8657 rev 3.00 page 15 of 34 december 12, 2014 figure 12. de mode: v in = 36v, v out = 12v, i out = 30ma, l = 4.7h, c out = 98f, f sw = 300khz (pulse skip operation) figure 13. forced pwm mode, v in =36v, v out = 12v, i out = 2.5a, l = 4.7h, c out = 98f, f sw = 300khz figure 14. forced pwm mode, v in = 36v, v out = 12v, i out = 1.0a, l = 4.7h, c out = 98f, f sw = 300khz figure 15. forced pwm mode, v in = 36v, v out = 12v, i out = 30ma, l = 4.7h, c out = 98f, f sw = 300khz figure 16. initialization to start-up: de mode, v in = 36v, v out = 12v, i out = 2.5a, l = 4.7h, c out = 98f, f sw = 300khz figure 17. initialization to start-up: de mode, v in = 36v, v out = 12v, i out = 0a, l = 4.7h, c out = 98f, f sw =300khz typical performance all the performance curves are taken from the evalua tion board (ISL78268eval1z) unless otherwise noted. (continued) 10s/div v out : 2v/div v in : 5v/div i l : 2a/div ph: 10v/div 2s/div i l : 2a/div ph: 10v/div v in : 5v/div v out : 2v/div i l : 2a/div ph: 10v/div v out : 2v/div v in : 5v/div 2s/div i l : 2a/div ph: 10v/div v out : 2v/div v in : 5v/div 10s/div ph: 20v/div comp: 1v/div clkout: v cc : 5v/div 2v/div 1ms/div 1ms/div ph: 20v/div comp: 1v/div clkout: v cc : 5v/div 2v/div
ISL78268 fn8657 rev 3.00 page 16 of 34 december 12, 2014 figure 18. initialization to start-up: forced-pwm mode, v in = 36v, v out = 12v, i out = 2.5a, l = 4.7h, c out = 98f, f sw = 300khz figure 19. initialization to start-up: forced-pwm mode, v in = 36v, v out = 12v, i out = 0a, l = 4.7h, c out = 98f, f sw = 300khz figure 20. soft-start (non-prebiased): de mode, v in = 36v, v out = 12v, i out = 2.5a, l = 4.7h, c out = 98f, f sw = 300khz figure 21. soft-start (non-prebiased): de mode, v in = 36v, v out = 12v, i out = 0a, l = 4.7h, c out = 98f, f sw =300khz figure 22. soft-start (non-prebiased): forced-pwm mode, v in = 36v, v out = 12v, i out = 2.5a, l = 4.7h, c out = 98f, f sw = 300khz figure 23. soft-start (non-prebiased): forced-pwm mode, v in = 36v, v out = 12v, i out = 0a, l = 4.7h, c out = 98f, f sw = 300khz typical performance all the performance curves are taken from the evalua tion board (ISL78268eval1z) unless otherwise noted. (continued) ph: 20v/div comp: 1v/div clkout: v cc : 5v/div 2v/div 1ms/div ph: 20v/div comp: 1v/div clkout: v cc : 5v/div 2v/div 1ms/div ph: 10v/div ss: 1v/div v out : 5v/div fb: 1v/div 500s/div ph: 10v/div ss: 1v/div v out : 5v/div fb: 1v/div 500s/div ph: 10v/div ss: 1v/div v out : 5v/div fb: 1v/div 500s/div ph: 10v/div ss: 1v/div v out : 5v/div fb: 1v/div 500s/div
ISL78268 fn8657 rev 3.00 page 17 of 34 december 12, 2014 figure 24. soft-start (prebiased): de mode, v in = 36v, v out =12v, i out = 0a, l = 4.7h, c out = 98f, f sw = 300khz figure 25. soft-start (prebiased): forced-pwm mode, v in =36v, v out = 12v, i out = 0a, l = 4.7h, c out = 98f, f sw = 300khz figure 26. load regulation figure 27. line regulation figure 28. transient response: de mode, v in = 36v, v out =12v, i out = 0.1a to 4.5a, l = 4.7h, c out = 98f figure 29. transient response: de mode, v in = 36v, v out =12v, i out = 1a to 3a, l = 4.7h, c out = 98f typical performance all the performance curves are taken from the evalua tion board (ISL78268eval1z) unless otherwise noted. (continued) ph: 10v/div ss: 1v/div v out : 5v/div fb: 1v/div 500s/div ph: 10v/div ss: 1v/div v out : 5v/div fb: 1v/div 500s/div 11.80 11.85 11.90 11.95 12.00 12.05 12.10 12.15 12.20 12.25 12.30 01 2 3 45 v out (v) i out (a) v in = 15v v in = 24v v in = 36v v in = 55v 11.80 11.85 11.90 11.95 12.00 12.05 12.10 12.15 12.20 12.25 12.30 10 20 30 40 50 60 v out (v) v in (v) i out = 0.1a i out = 1a i out = 3a ph: 20v/div i l : 2a/div v out (ac) : 500mv/div comp: 1v/div 500s/div v out (ac) :200mv/div comp: 500mv/div (1.5v dc-ffset) 500s/div ph: 20v/div i l : 2a/div
ISL78268 fn8657 rev 3.00 page 18 of 34 december 12, 2014 figure 30. transient response: forced-pwm mode, v in =36v, v out =12v, i out = 0.1a to 4.5a, l = 4.7h, c out =98f figure 31. transient response: forced-pwm mode, v in =36v, v out =12v, i out = 1a to 3a, l = 4.7h, c out = 98f figure 32. hiccup: acl, v in = 30v, v out =12v, r imon = 156k ? figure 33. internal ldo load regulation: v in = 36v, t a = +25c figure 34. average constant output current control, v in = 20v, v out (setting) = 12v, c imon = 1nf, r imon =130k ? , acl = 4.05a, r l = 5.0 ? to 2.0 ? , f load = 10hz, duty of load change = 50% figure 35. average constant output current control, v in = 36v, v out (setting) = 12v, c imon = 1nf, r imon =130k ? , acl = 4.05a, r l = 5.0 ? to 2.0 ? , f load = 10hz, duty of load change = 50% typical performance all the performance curves are taken from the evalua tion board (ISL78268eval1z) unless otherwise noted. (continued) ph: 10v/div i l : 3a/div v out (ac) :200mv/div comp: 500mv/div (1.5v dc-offset) 500s/div ph: 10v/div i l : 3a/div v out (ac) :200mv/div comp: 500mv/div (1.5v dc-offset) 500s/div i l : 3a/div ss: 2v/div ph:20v/div v out : 5v/div 100ms/div 560ms 0 1 2 3 4 5 6 0 v out (v) i out (a) 0.05 0.10 0.15 0.20 0.25 0.30 ph: 20v/div i out : 1a/div v out : 5v/div imon/de: 0.5v/div 20ms/div ph: 20v/div i out : 1a/div v out : 5v/div imon/de: 0.5v/div 20ms/div
ISL78268 fn8657 rev 3.00 page 19 of 34 december 12, 2014 figure 36. average constant output current control, v in = 20v, v out (setting) = 12v, c imon = 1nf, r imon =130k ? , acl = 4.05a, r l = 2.3 ? , start-up with fixed r l figure 37. average constant output current control, v in = 36v, v out (setting) = 12v, c imon = 1nf, r imon =130k ? , acl = 4.05a, r l = 2.3 ? , start-up with fixed r l typical performance all the performance curves are taken from the evalua tion board (ISL78268eval1z) unless otherwise noted. (continued) ph: 20v/div i out :1a/div v out : 5v/div imon/de: 0.5v/div 20ms/div ph: 20v/div i out : 1a/div imon/de: 0.5v/div 20ms/div v out : 5v/div
ISL78268 fn8657 rev 3.00 page 20 of 34 december 12, 2014 operation description the ISL78268 is an automotive graded (aec-q100 grade-1) single-phase synchronous buck controller with integrated high/low side 2/3a mosfet driver s. it supports a wide operating input voltage range of 5v to 55v and up to 60v at v in when not switching. the device also provides the features of selectable diode emulation mode for the higher efficiency operation in light load conditions, average constant output current controls, and several protection features such as input overvoltage protection, output overvoltage protection, cycle-by-cycle current limit and protections, and thermal protection. details of the functions are described in the following. synchronous buck in order to improve the effi ciency, the ISL78268 employs synchronous buck architecture. in a synchronous buck, the lg output drives the synchronous lo w-side mosfet, which replaces the freewheeling diode and improves the power losses by the voltage drop of the freewheeling diode while the high-side mosfet is off. the lg signal is complementary to the ug signal. the ug signal is powered from a charge pump that generates a voltage between boot and ph. an external diode from pvcc to boot charges an external capaci tor between boot and ph when lg is high and ph is low. the capacitor provides the power to drive ug high. boot rises with ph and maintains the voltage to drive ug as the bootstrap diode is reverse biased. adaptive dead-time control the ug and lg drivers are desi gned to have an adaptive dead-time algorithm that opti mizes operation with varying mosfet conditions. in this algorithm, the device detects the off timing of external mosfets whic h is turning off via the gate driver output voltage. the isl 78268 adds internally fixed 55ns dead-time before turning on the target gate driver. this algorithm helps to prevent shoot-through current at the switching of external mosfets and also opti mizes the total dead-time to maximize the efficiency. operation initialization and soft-start prior to the converter initializat ion, vin and vcc need to be supplied within the valid voltage range and the en pin needs to be biased to logic high. when thes e conditions are provided, the controller begins soft-start. once the output voltage is within the proper window of output regulation, v pgood is asserted logic high. figure 38 shows the ISL78268 internal start-up timing diagram from the power-up to soft-start and valid pgood assertion. as shown on figure 38 , there are 5 time intervals before the soft-start is initialized, they are specified as t 1 through t 5 . after soft-start is initiated, there ar e 5 time intervals indicated as t 5 through t 10. the descriptions for each time interval are as follows: t 1 - t 2 : the internal enable comparator holds the ISL78268 in shutdown until the en pin voltage (v en ) rises above 1.2v (typ) at the time of t 1 . during t 1 - t 2 the internal ldo output voltage at the pvcc pin (v pvcc ) will gradually increase until t 2 when it reaches the internal power-on reset (p or) rising threshold which is 4.5v(typ). t 2 - t 3 : during t 2 - t 3 time, the ISL78268 will go through a self-calibration process to determine the pin connections (hic/latch, imon/de) for the operation mode selections. the time duration for t 2 - t 3 is typically 170s. t 3 - t 4 : during this period, the ISL78268 will wait until the internal pll circuit is locked to the preset oscillator frequency set by the resistor on fsync or the external clock at fsync. when pll locking is achieved at t 4 , the oscillator will ge nerate output at the clk_out pin. the time duration for t 3 - t 4 depends on pll_comp pin configuration. the pll is compensated with a series resistor-capacitor r pllcmp , c pllcmp1 from the pll_comp pin to gnd and a capacitor c pllcmp2 from pll_comp to gnd. typical values are r pllcmp = 3.24k , c pllcmp1 = 6.8nf, c pllcmp2 = 1nf. with this pll_comp compensation, the time duration for t 3 - t 4 is around 0.8ms. t 4 - t 5 : after the pll locks the frequency at t 4 , the system is preparing to soft-start. the ISL78268?s unique feature will prebias the v ss based on v fb voltage during this time. the duration time for t 4 - t 5 is around 50s. during t 4 - t 5 drivers remain off. t 5 - t 6 : after t 5 , the soft-start circuit starts to ramp up from the prebiased vfb. at the same time, the comp pin voltage starts to ramp up also. the ug driver will be enabled at t 5 . however, before t 6 , comp is still below the peak current mode control ramp offset, the drivers will not be switching. during soft-start period t 5 - t 10 , the device will operate with diode emulation mode and keep lg driver off. t 6 - t 7 : if the fb voltage (vfb) is below 0.4v (typ), the device operates at fixed minimum fr equency (50khz (typ)) with minimum high-side mosfet on-time. when vfb reaches figure 38. circuit initialization and soft-start en 1.2v por_r pvcc/vcc pllcomp clkout ug lg ph comp comp_ramp_offset vfb ss vfb = 0.4v t 1 t 2 t 3 t 4 t 5 t 6 t 8 t 9 t 7 t 10 pgood
ISL78268 fn8657 rev 3.00 page 21 of 34 december 12, 2014 0.4v (typ), the switching frequency will change to the target frequency gradually and the high-side mosfet on-time will be controlled by the pwm control loop. if the prebiased fb voltage is above 0.4v (typ), the device starts up with the target switching frequency. if fb volt age is >0.4v the time t 6 - t 7 is negligible. t 6 - t 8 : at t 6 , comp is above the peak current mode control ramp offset, the drivers starts switching. output voltage ramps up while fb voltage is following ss ramp during this soft-start period. at t 8 , output voltage reaches the regulation level and fb voltage reaches 1.6v (typ). t 7 - t 10 : ss pin voltage continues ramping up until it reaches ss clamp voltage 3.4v (typ) at t 9. the soft-start period will be completed at t 10 which is 0.5ms (typ) after the t 9. when the soft-start completes, the device operates in the operation mode selected by the imon/de configur ation. if the forced pwm mode is selected, the device operates in full synchronous rectification. if the diode emulation mode (de mode) is select ed, the device will be able to operate in de mo de, i.e., turn-off low-side mosfet when the inductor current reache s zero to prevent the negative current and improves the efficiency. at the end of soft-start period t 10, the pgood open-drain follows the comp and inductor current ramp signal relations. pin is released and will be pulled up by the external resistor. enable to enable the device, the en pin needs to be driven higher than 1.2v (typ.) by the external enab le signal or resistor divider between vin and gnd. the en pin has an internal 5m (typ) pull-down resistor. also, this pin internally has a 5.2v (typ) clamp circuit with 5k (typ) resistor in series to prevent excess voltage applied to the internal circuits . when applying the en signal using resistor divider from vin, internal pull-down resistance needs to be considered. also the re sistor divider ratio needs to be adjusted as its en pin input voltage may not exceed 5.2v. to disable or reset all fault status , the en pin needs to be driven lower than 1.1v (typ). when the en pin is driven to low, the ISL78268 turns off all of the bloc ks to minimize the off-state quiescent current. clock generator and synchronization internal clock frequency setting the switching frequency is determined by the selection of the frequency-setting resistor, r fsync , connected from the fsync pin to gnd. equation 1 and figure 40 provide the relation between r fsync and switching frequency. for stable operation of the device, it is recommended to set the f sw between 50khz to 1.1mhz. where f sw is the switching frequency of the device. figure 41 shows the block diagram of the clock generator block. the fsync pin is biased at 0.5v (typ). the 0.5v at fsync creates a constant current with r fsync . the current is fed to the internal oscillator to generate the internal base clock. this internal base clock is reshaped with the phase lock loop (pll) circuitry and the output of pll will be used as the main clock of the device. figure 39. enable block en from external en control vcc 5m 5.2v clamp - + 1.2v to internal circuits 5k vin ?? 10 x 0.5 f sw --------- - 5.0x10 8 C C ?? ?? = figure 40. r fsync vs f sw 0 200 400 600 800 1000 1200 1400 0 50 100 150 200 250 300 f sw (khz) r fsync (k) figure 41. clock genera tor and external clock synchronization block r fsync fsync 0.5v v ih(rise) > 3.5v v il(fall) < 1.5v pll internal oscillator vcc - + pfd vco internal base clock external clock clock pll_comp r pllcmp c pllcmp1 c pllcmp2
ISL78268 fn8657 rev 3.00 page 22 of 34 december 12, 2014 synchronization with external clock the ISL78268 contains a pll circuitry and has frequency synchronization capability by simp ly connecting the fsync pin to an external square pulse waveform. the pll block detects the rising edge of external clock and synchronizes it with the rising edge of ug. the delay time of ug rising from the external clock rising edge is 325ns (typ). the fsync pin has special thresholds to detect the external clock. the input high level of external clock should be higher than 3.5v and low level should be lower than 1.5v. when continuous external clock pulse is applied while operating with internal clock which is determined by r fsync , this device synchronizes with the external clock gradually and continues its switching. however, when the external clock is removed for a certain period (~6ms), the device will stop its switching and restart from the initialization/soft-start proce ss after about a 50ms interval. the pll is compensated with a series connected resistor and capacitor (r pllcmp and c pllcmp ) from the pll_comp pin to gnd and a capacitor (c pllcmp2 ) from pll_comp to gnd. for stable operation, re commended to set r pllcmp = 3.24k , c pllcmp1 = 6.8nf, c pllcmp2 = 1nf. the typical lock time for this case will be around 0.8ms. the clkout pin provides a square pulse waveform at the switching frequency. the amplitude is gnd to vcc with 270ns (typ) pulse width, and the rising edge is 180 shifted from the rising edge of ug. soft-start soft-start is implemented by an internal 5a current source charging the soft-start capacitor (c ss ) at ss to gnd. the voltage on the ss pin controls the refere nce voltage for the fb pin during soft-start. when starting up the system while the output voltage is remaining (prebiased), a prebias circuit charges the c ss capacitor to the same voltage as fb voltage before soft-start begins. this allows more accurate correlation between the soft-start ramp time and the output voltage. assuming no prebiased output condition, the soft-start ramp time is: where v ref is the 1.6v reference. assuming no load condition, the average inductor current i l_softstart to charge the output capacitors from 0v to final regulation voltage within soft-start time t ss can be estimated as: if start-up with full load is required, the total inductor average current at the soft-start period is the sum of full load current and i l_softstart . based on this consideration, enough soft-start time should be set to make sure over current protection is not tripped. at the beginning of soft-start, if the prebiased v fb voltage is lower than 0.4v (typ), the device is forced to switch at 50khz (typ) with minimum on-time of high-side mosfet. when v fb reaches 0.4v (typ) or higher, the device operates with normal switching frequency and on-time. if the prebiased vfb voltage is higher than 0.4v (typ) at the starting of soft-start, the device starts with normal switching frequency from the beginning. the soft-start period will be finished when the ss pin voltage reaches its clamp voltage (3.4v typ) with a 0.5ms (typ) additional interval. at the end of soft-start period, the pull-down of the pgood pin will be released and this pin will be pulled up by external resistor, which will be biased to vcc or external logic supply level. while in soft-start period, the device operates in diode emulation mode to prevent undesired negative current at inductor from output. in this period, regardless of the configuration of imon/de pin, i.e., either forced pwm mode or diode emulation mode is selected, only the high-side mosfet will be switched and low-side mosfet will be kept off. bootstrap for high-side nmos drive to turn on the high-side mosfet properly, the ISL78268 employs a bootstrap circuit using an external boot capacitor (c boot ) and diode (d bt ). at the time the high-side mosfet turns off, to maintain the current on the inductor, the ph node will go down to gnd level at low-side mosfet turn on. while in this low-side mosfet on period, the diode connected from pvcc to boot capacitor will be forward biased and charge up the boot capacitor. when the low-side mosfet is turned off and the high-side mosfet is turned on after dead-time, the ph node goes up to vin level and the boot pin bias is vin + pvcc - v f to drive the high-side driver circuitry. boot refreshing in order to keep sufficient supply voltage for the high-side driver circuit operation, the ISL78268 has a boot-refreshing circuit. when the boot capacitor voltage becomes lower than 3.3v (typ), the low side transistor is forced to turn on with its minimum on time to charge the boot capacitor. the boot refreshing will occur at the beginning of soft-start and pulse skipping operation at very light load conditions. (eq. 2) t ss v ref c ss 5 ? a ----------- = ------------- = figure 42. soft-start block c ss ss v ref = 1.6v soft-start control logic vcc to pwm comparator comp fb 5a ss_done ss_prebias - + - + +gm - + 0.4v - + 0.4v to pwm control & pgood control vout comp 3.4v clamp
ISL78268 fn8657 rev 3.00 page 23 of 34 december 12, 2014 minimum off-time consideration to ensure the charging of the boot capacitor, the device has internally fixed minimum off time (t minoff ) for the high-side mosfet. just after the high-side mosfet turns off, the ph node goes down to gnd level and boot capacitor will be charged from pvcc via an external diode (schottky diode is recommended). however, when an nmos with large q g is selected to support heavy load application, the internally fixed t minoff may not be enough to charge the boot capacitor sufficiently. for this case, it is recommended to adjust the switching frequency or input voltage as the system has sufficient off time of high-side transistor. pwm operation the switching cycle is defined as the time between ug pulse initiation signals. the cycle time of the pulse initiation signal is the inversion of the switching frequency set by the resistor between the fsync pin and ground. the ISL78268 uses peak curr ent mode control. the pwm operation is initialized by the clock from the oscillator. the high-side mosfet is turned on (ug) by the clock at the beginning of a pwm cycle and the inductor current flows in the high-side mosfet and ramps up. when the sum of the current sense signal (through i sen1 current sense amplifier) and the slope compensation signal reaches the error amplifier output voltage, the pwm comparator is triggered and ug is turned off to shut down the high-side mosfet. the high-side mosfet stays off until the next clock signal comes for the next cycle. after the high-side mosfet is turned off, the low-side mosfet turns on with the fixed dead-time. the off timing of low-side mosfet is determined by either the next high-side on timing at next pwm cycle or when the inductor current become zero if the diode emulation mo de is selected. to prevent undesired shoot-through current at external high-side and low-side mosfets, the device has adaptive dead-time control and internally fixed de ad-time. the internally fixed dead-time is typically 55ns, for both high-side to low side and low-side to high-side switching transition. the output voltage is sensed by a resistor divider from v out to the fb pin. the difference between the fb voltage and 1.6v (typ) reference is amplified and compensated to generate the error voltage signal at the comp pin th at is used for pwm generation circuits. current sensing the ISL78268 has two current sens e amplifiers: one for high-side mosfet peak current sensing for pwm control and overcurrent protections, and the other for output inductor current sensing for average current control and diod e emulation timing control. current sense amplifier 1 (csa1) the current-sense amplifier (csa1) is used to sense the inductor current in the current-sense resistor placed in series with the high-side mosfet. the sensed current information (i sen1 ) is used for peak current mode control and overcurrent protection. peak current mode control is implemented using csa1 in the pwm control loop as described in ? pwm operation ? . the cycle-by-cycle peak current limit (oc1) is implemented by comparing i sen1 with an 70a threshold. at the peak current limit comparator threshold, the pwm pulse is terminated. during an overload condition when i sen1 reaches 93a (oc2 threshold), the ic enters into latch-off or hiccup mode, which is defined by the hic/latch pin configuration. if latch-off mode is selected, the device stops switching when oc2 is tripped and will not restart until the en or vin is toggled. if hiccup mode is selected, the pwm is disabled for 500ms (typ) before beginning a soft-start cycle. three consecutive oc2 faults are required to enter hiccup or latch-off. oc2 hiccup or latch-off is enabled during soft-start and normal operating modes. current sense amplifier 2 (csa2) the current-sense amplifier (csa2) is used to sense the continuous (not pulsing as in r sen1 ) inductor current either by dcr sensing method or using a sens e resistor in series with the inductor for more accurate sensing. the sensed current signal is used for three functions: ? average constant current control ? diode emulation ?average oc protection the isen2p voltage is also used to monitor the minimum output voltage. under the overload cond ition (oc1) or under the average constant current control, if the voltage become lower than about 1.2v (typ), the device stops switching and enters latch-off/ hiccup mode. if these three functions are not required in the application, csa2 should be connected to vcc (or vin). sense resistor current sensing a sense resistor can be placed in series with the inductor. as shown in figure 44 , the ISL78268 senses the voltage across the sense resistor. csa1 is used to sense the high-side mosfet?s current. the sense resistor is placed between the input capacitors and the high-side mosfet. csa2 is used to sense the inductor current. a sense resistor is placed between the inductor and the output capacitors. the voltage on the isen(n)p and isen(n)n of the current sense amplifier are forced to be equal. the voltage across r set(n) is equivalent to the voltage drop across the r sen(n) resistor. the figure 43. output boot control vin boot pvcc ug ph lg pgnd level shift dead time control pvcc - + 3.3v to boot refresh control pwm signal d bt r c c boot l r sense vout to current sense amp
ISL78268 fn8657 rev 3.00 page 24 of 34 december 12, 2014 resulting current into the isen(n)p pin is proportional (scaled) to the current in r sen(n) . equation 4 is derived as: where r set(n) is the sum of r set(n)a and r set(n)b in figure 44 . isen(n)p and isen(n)n have eq ual bias current (112a typ) therefore, the resistors r bias(n) and r set(n) should be matched to prevent offset. to prevent noise injection from switching currents, it is recommended to place a filter capacitor in between the r set resistors. typically, 220pf ceramic capacitor is used when the r set(n) is 665 . inductor dcr sensing an inductor has a distributed resistance as measured by the dcr (direct current resistance) parameter. the inductor dcr can be modeled as a lumped quantity, as shown in figure 45 , equation 5 shows the s-domain equivalent voltage across the inductor v l . a simple r-c network across the inductor can extract the dcr voltage, as shown in figure 45 . the voltage on the capacitor v cdcrs , can be shown to be proportional to the channel current i l , see equation 6 . if the c dcrs is selected so 2* ? *f sw *c dcrs is much greater than 1/r set , the 1/r set will be negligible. also, if the r-c network components are selected such that the time constant (r dcrs *c dcrs ) matches the inductor time constant (l/dcr), the voltage across the capacitor v cdcrs is equal to the voltage drop across the dcr, i.e., propor tional to the inductor current. with the internal current sense amplifier, the capacitor voltage v cdcrs is replicated across the sense resistor r set2 . therefore, the current flow into the isen2p pin is also proportional to the inductor current. equation 7 shows the relation between sensed current i sen2 and inductor current (i l) when dcr sensing is used. adjustable slope compensation a buck converter operating in peak current mode requires slope compensation when the duty cycle is larger than 50%. it is advisable to add slope compensation when the duty cycle is approximately 30% or more since a transient load step can push the duty cycle higher than the steady state level. when slope compensation is too low, the converter can suffer from subharmonic oscillation, which may result in noise emissions at half the switching frequency. on the other hand, overcompensation of the slope may reduce the phase margin. therefore, proper design of the slope compensation is needed. the ISL78268 features adjustab le slope compensation by setting the resistor value r slope from the slope pin to gnd. figure 46 shows the block diagram related to slope compensation. for current mode control, in theory we need the compensation slope m sl to be larger than 50% of the inductor current down ramp slope m b . equation 8 shows the resistor value at slope pin to create a compensation ramp. where k is the selected gain of compensation slope over inductor down slope. for example, k = 1 gives the r slope value generating a compensation slope equal to inductor current down ramp slope. theoretically, the k needs to be larger than 0.5 and in general, more than 1.0 is used in the actual application. i sen n ?? i r sen n ?? r se nn ?? r se tn ?? ---------------------- - ? = (eq. 4) figure 44. sense resistor current sensing a v = 1 112a 112a a v = 1 112a 112a r set1a r set1b r set2a r set2b r bias1a r bias1b r bias2a r bias2b isen1p isen1n isen2p isen2n r sen1 r sen2 l c in ug lg v out vin i l i sen1 i sen2 ISL78268 internal circuits + - + - c out i sen1 + 112a isen2+112a csa1 csa2 112a 112a + ? ?? ? = (eq. 5) v cdcrs s l dcr ----------- - ? 1 + ?? ?? dcr i l ? ?? ? r dcrs 1 r set ------------ - sc dcrs ? + ?? ?? 1 + ? --------------------------------------------------------------- --------------------- = (eq. 6) i sen2 i l dcr r set2 ---------------- ? = (eq. 7) figure 45. inductor dcr current sensing a v = 1 112a 112a to csa1 r set2 r bias2 isen2p isen2n r sen1 l c in ug lg v out vin i l i sen2 ISL78268 internal circuits + - +- c out csa2 dcr r dcrs c dcrs + - - + 112a ------------------------------------------------- - ? ?? = (eq. 8)
ISL78268 fn8657 rev 3.00 page 25 of 34 december 12, 2014 light load efficiency enhancement for switching mode power supplies, the total loss is related to both the conduction loss and the switching loss. the conduction loss dominates at heavy load while the switching loss dominates at light load condition. the isl7 8268 has the option to be set in cycle-by-cycle diode emulation mode and pulse skipping features to enhance the light load efficiency. imon/de is used to select de (diode emulation) mode. when the imon/de is connected to an extern al resistor or shorted to gnd, the de mode is selected. also, if imon/de pin is pulled up to vcc level, the device operates in forced pwm mode. to achieve diode emulation mode , the current sense amplifier csa2 is used to sense the output inductor current either by dcr sensing or an accurate current shunt resistor. diode emulation at light load condition when de mode is selected, if the inductor current reaches discontinuous conduction mode (dcm) operation, the ISL78268 controller will turn off the low-side mosfet and enter into diode emulation mode. by utilizing the cycle-by-cycle diode emulation scheme, negative current is prevented and the effi ciency is improved from the smaller rms current in the power stage. while in soft-start period until the pgood pull-down is released, the low-side mosfet is forced off (in either cases of de mode or forced pwm mode is selected). pulse skipping at deep light load condition if the converter enters diode emulation mode and the load is further reduced, comp voltage becomes lower than the minimum threshold and the device skips the pulses to increase the deep light load efficiency. average constant current control in normal pwm operation, the pwm pulse is terminated when the sensed peak current reaches the error amplifier control voltage. but some applications, such as charging a battery, may desire constant output current control instead of output voltage control. to support such requirements, ISL78268 provides the average constant current control loop to control the average current up to the fb regulated output voltage. average constant current control operates in the range of approximately 25% to 100% of targ eted output voltage. this is due to the function described in the soft-start sequence (t 6 -t 7 ) when the fb voltage (vfb) is below 0.4v and the device operates at 50khz (typ) with minimum high-side mosfet on time. the imon/de pin serves to monito r the average current that is used for average constant current control and average overcurrent protection (avgocp). the current sense amplifier 2 (csa2) output current, i sen2 , which is representing the output current (see figure 44 for r sen and r set positions) is sourcing out from this pin. equation 9 describes the relation between output current (i out ) and imon/de pin current (i imon ). an rc network should be connected between the imon/de pin and gnd, such that the ripple current signal can be filtered out and converted to a voltage signal to represent the averaged output current. the time constant of the rc network should be on the order of 10 to 100 times slower than the voltage loop bandwidth so that the programmable current limit circuit does not interfere with the control loop stability. the imon/de pin voltage v imon can be calculated as equation 10 . when the imon/de pin voltage is at 1.6v (typ), the average constant output current control l oop on the device limits the on time of high-side mosfet to ke ep the output current constant. while the average constant output current control is working, the output voltage may become lowe r than preset output voltage because of the lowered duty cycle. equation 11 shows the r imon for the desired average output current. figure 46. slope compensation block vramp = (isen1+isl)*rg isl vramp i slope i sen1 m b m sl m a m a1 = m a + m sl r slope slope vrefsl = 0.5v vcc - + vin vout vramp - + r g i sen1 i slope isl r set r bias r sen isen1p isen1n c sl vsl on while ug on on while lg on isl1 = n*islope m a1 = m a + m sl ------------- - ? 68 10 ? 6 C + ?? ?? ?? 0.125 ? = (eq. 9) v imon i imon r imon ? = (eq. 10) r imon 12.8 i out r sen r set ------------- - 68 10 6 C ? + ? -------------------------------------------------------------- - = (eq. 11)
ISL78268 fn8657 rev 3.00 page 26 of 34 december 12, 2014 fault monitoring and protection the ISL78268 actively monitors inpu t/output voltage and current to detect fault conditions. fault moni tors trigger protective measures to prevent damage to the load. pgood signal the power-good indicator pin (pgood pin) is provided for fault monitoring. the pgood pin is an open-drain logic output to indicate that the soft-start period is completed and the output voltage is within the specified range. an external pull-up resistor (10k to 100k ) is required to be connected between pgood pin and vcc or external power supply (5.5v max). this pin is pulled low during soft-start. the pgood pin is released high after the voltage on ss pin reaches ss clamp voltage (3.4v typ) and after a 0.5ms (typ) delay. pgood will be pulled low with a 10s (typ) blanking filter when outp ut uv, or ov fault, or vin ov fault occurs, or en is pulled low. the pgood will be released high after the 0.5ms (typ) delay when the above faults are removed. hiccup/latch-off operation as a response to fault detection, either hiccup or latch-off mode can be selected by the configuration of the hic/latch pin. when the hic/latch pin is pulled high (vcc), the fault response will be hiccup mode. when hic/latch pin is pulled low (gnd), the fault response will be in latch-off mode. in hiccup mode, the device will stop switching when a fault condition is detected, and restart from soft-start after 500ms (typ). this operation will be repeated until fault conditions are completely removed. in latch-off mode, the device will stop switching when a fault condition is detected and be kept off even after fault conditions are removed. either toggling the en pin or cycling vin below the por threshold will restart the system. input overvoltage protection the ISL78268 features overvoltage (ov) fault protection for the input supply. when vin is higher than 58v (typ), the ug and lg gate drivers are disabled and the pgood pin is pulled low. there is a 10s (typ) transient filter to prevent noise spikes from triggering input ov. the input ov response can be selected as latch-off or hiccup. the recovery from output overvolt age in hiccup or latch-off is the same as described in ? hiccup/latch-off operation ? . if the hiccup mode is selected, the input ov recovery threshold is below 55v (typ). output undervoltage detection the ISL78268 detects the output undervoltage condition. the output undervoltage threshold is set at 87.5% (typ) of the 1.6v fb reference voltage. when the fb voltage is below the undervoltage threshold for more than 10s (typ ), the pgood pin is pulled down. if the output voltage rises above the undervoltage recovery threshold of 90.5% (typ) of fb re ference voltage, pgood is pulled up after 0.5ms (typ) delay. during an undervoltage condition, the device continues normal operation unless either oc2, avgocp, input ovp, or thermal shutdo wn protection is triggered. output overvoltage detection/protection the ISL78268 output overvoltage detection circuit is active after soft-start is completed. the output voltage is monitored at the fb pin and the output overvoltage trip point is set to 115% (typ) of the fb reference voltage. if the output overvoltage condition is longer than 10s (typ) blanking time, the pgood pin is pulled down and the controller moves into hiccup or latch-off mode. the recovery from output overvoltage in hiccup or latch-off is the same as described in ? hiccup/latch-off operation ? . if the hiccup mode is selected, the output ov recovery threshold is 112% (typ) of fb reference voltage. cycle-by-cycle peak overcurrent limiting/protection ISL78268 features cycle-by-cycle peak overcurrent protections by sensing the peak current at csa1. the ic continuously compares the csa1 output current (i sen1 calculated from equation 4 ), which is proportional to the current flowing at current sense resistor1 (r sen1 ) with two overcurrent protection threshold, 70a for oc1 and 93a for oc2. the oc1 and oc2 levels are defined as equations 12 and 13 . if i sen1 reaches oc1 threshold, the high-side mosfet is turned off. this reduces the converter duty cycle which decreases the output voltage. after oc1 protection has reduced the controller down to minimum duty cycle, if the output current increases to the oc2 threshold for three consecutive sw itching cycles, the controller disables the gate drivers and enters hiccup or latch-off mode. the recovery from oc2 in hiccup or latch-off is the same as described in the ? hiccup/latch-off operation ? . the oc1 cycle-by-cycle current limiting and oc2 protection are active during soft-start an d normal oper ation period. average overcurrent protection when the average constant current control loop is active, the ic also provides average overcurrent protection. when output current increases even the duty cycle becomes minimum by the average constant current control loop, the v imon voltage rises above 1.6v. if v imon reaches 2v (typ), the ISL78268 stops gate drivers and enters into the hiccup mode. this provides additional safety for the voltage regulator. equation 14 provides the r imon value for the desired average overcurrent protection level i ocpavg . the average overcurrent protection (2v ref at imon/de) will not be asserted until the soft-start period is completed. (eq. 12) i oc1 70 10 6 C r set r sen ------------- - ? ? = C r set r sen ------------- - ? ? = ------------- - 68 10 6 C ? + ? --------------------------------------------------------------- ----------- = (eq. 14)
ISL78268 fn8657 rev 3.00 page 27 of 34 december 12, 2014 negative current limit when operating in forced pwm mo de operation in light load, the negative current from the output capacitor to gnd flows by the turn on of the low-side mo sfet. the ISL78268 provides cycle-by-cycle negative current limit to prevent excess negative current. equation 15 shows the peak negative current limit (i neglim ) threshold. thermal protection if the junction temperature reac hes +160c (typ), the ISL78268 switching will be disabled and enter into hiccup or latch-off mode. when hiccup mode is selected, a 15c (typ) hysteresis insures that the device will not restart until the junction temperature drops below +145c (typ) in hiccup mode. internal 5.2v ldo the ISL78268 has an internal ldo with input at vin and a fixed 5.2v/100ma output at pvcc. a 4.7f, 10v or higher x5r or x7r rated ceramic capacitor is recommended between pvcc to gnd. the output of this ldo is mainly used as the bias supply of the internal circuitry. to provide a quiet power rail to the internal analog circuitry, it is recommend ed to place rc filter between pvcc and vcc. a 10 resistor between pvcc and vcc and at least 1f ceramic capacitor from vcc to gnd are recommended. output current limitation of internal ldo the internal ldo tolerates an input supply range of vin up to 55v (60v absolute maximum). however, the power losses at the ldo need to be considered, especially when the gate drivers are driving external mosfets with a large gate charge. at high v in , the ldo has significant power dissipation that may raise the junction temperature where the thermal shutdown occurs. figure 47 shows the relationship between maximum allowed ldo output current and input volt age. the curves are based on +39c/w thermal resistance ? ja of the package. the maximum ldo current can be supplemented with an external pnp transistor as shown in figure 48 . the advantage is that the majority of the power dissipation can be moved from the ISL78268 to the external transistor. choose r s to be 68 so that the ldo delivers about 10ma when the external transistor begins to turn on. the external circ uit increases the minimum input voltage to approximately 6.5v. application information there are several ways to define the external components and parameters of buck regulators. this section shows one example of how to decide the parameters of the external components based on the typical application schematics shown in figure 4 on page 8 . in the actual application, th e parameters may need to be adjusted and also a few more ad ditional compon ents may need to be added for the application specific noise, physical sizes, thermal, testing and/or other requirements. output voltage setting the output voltage (v out ) of the regulator can be programmed by an external resistor divider set from v out to fb and fb to gnd. v out can be defined as: in the actual application, the resistor value should be decided by considering the quiescent current requirement and loop response. typically, between 10k to 30k will be used for the rfb0. switching frequency switching frequency may be determined by considering several requirements such as system leve l response time, solution size, emc/emi limitation, power dissipation and efficiency, ripple noise level, minimum and maximu m input voltage range, etc. higher frequency may improve the transient response and help to minimize the solution size. however, this may increase the switching losses and emc/emi concerns. thus, a balance of these parameters are needed when deciding the switching frequency. once the switching frequency is decided, the frequency setting resistor (r sync ) can be determined by equation 1 . i neglim 50 C 10 6 C ? r set r sen ------------- - ? = (eq. 15) figure 47. power derating curve 0 20 40 60 80 100 120 160 5 152535455060 i ldo(max) (ma) v in (v) 140 10 20 30 40 55 t a = +125c t a = +75c t a = +25c figure 48. supplementing ldo current vin pvcc vin pvcc ISL78268 rs ------------- + ?? ?? ?? ? = (eq. 16)
ISL78268 fn8657 rev 3.00 page 28 of 34 december 12, 2014 output inductor selection while the buck converter is operating in stable continuous conduction mode (ccm), the output voltage and on-time of the high-side transistor is determined by equation 17 : where t is the switching cycle (1/f sw ) and d = t on /t is the on-duty of the high-side transistor. under this ccm condition, the in ductor ripple current can be defined as equation 18 : from the previous equations, the inductor value will be determined as equation 19 : in general, once the inductor value is determined, the ripple current varies by the input voltage. at the maximum input voltage, the on-duty becomes minimum and the ripple current becomes maximum. so, the minimum inductor value can be estimated from equation 20 . in dc/dc converter design, this ripple current will be set around 20% to 50% of maximum dc ou tput current. a reasonable starting point to adjust the induct or value will be around 30% of the maximum dc output current. increasing the value of inductor reduces the ripple current and thus ripple voltage. however, the large inductance value may reduce the converter?s response ti me to a load transient. also, this reduces the ramp signal and may cause a noise sensitivity issue. under stable operation, the peak current flow in the inductor will be the sum of output current and 1/2 of ripple current. this peak current at maximum load condition must be lower than the saturation current rating of the inductor with enough margin. in the actual design, the largest peak current may be observed at the start-up or heavy load transient. therefore, the inductor?s size needs to be determined with the consideration of these conditions. in addition, to avoid exceeding the inductor?s saturation rating, it is recommended to set the ocp trip point between the maximum peak current and the inductor?s saturation current rating. output capacitor to filter the inductor current ripples and to have sufficient transient response, an output capacitor is required. the current mode control loop allows the usage of lower esr ceramic capacitors and thus enables smaller board layout. electrolytic and polymer capacitors may also be used. however, additional consideration may be needed to use the ceramic capacitors. while the ceramic capacitor offers excellent overall performance and reliabilit y, the actual capacitance may be considerably lower than the advertised value if used dc biased condition. the effective capacitance can be easily 50% lower than that of the rated value. the following are equations for the required capacitance value to meet the desired ripple voltage level. additional capacitance may be used to lower the ripple voltage and to improve transient response. for the ceramic capacitor (low esr): where ? i l is the inductor?s peak-to-peak ripple current, f sw is the switching frequency and c out is the output capacitor. required minimum output capaci tance based on ripple current will be: if using electrolytic capacitors, the esr will be the dominant portion of the ripple voltage. so, to reduce the ripple voltage, reduce the ripple current with increasing the inductor value or use multiple capacitors in parallel to reduce the esr. the other factor which may affect the selection of the output capacitor will be the transient response. to estimate the capacitance value related to tran sient response, a good starting point is to determine the allowable overshoot in v out if the load is suddenly reduced. in this case , energy stored in the inductor will be transferred to c out and causing its voltage rise. equation 25 determines the required output capacitor value in order to achieve a desired overshoot level relative to the regulated voltage. where v outmax /v out is the relative maximum overshoot allowed during the removal of the load. after calculating the required capacitance for both ripple and transient needs, choose the larger of the calculated values as the output capacitance. to keep enough capacitance over the biased voltage and temperature range, a good quality capacitor such as x7r or x5r is recommended. input capacitor depending upon the system inpu t power rail conditions, the aluminum electrolytic type capacitor is normally used to provide the stable input voltage and restrict the switching frequency pulse current in small areas over the input trace for better emc performance. the input capacitor should be able to handle the rms current from the switching power devices. v out vin t on t -------- - vin d ? = ? = (eq. 17) i l(p-p) t on vin v out C l ---------------------------- - t off v out l ------------ - ? = ? = (eq. 18) l vin v out C f sw ---------------------------- - v out vin ------------ - ? = (eq. 19) l min vin max v out C f sw il max ? ? ------------------------------------- - v out vin max ------------------- - ? = (eq. 20) i l i l(p-p) 2 -------------- - i out ? = (eq. 21) v outripple i l ? 8f sw c out ?? ----------------------------------- - = (eq. 22) c outmin i l ? 8f sw v outmin ?? --------------------------------------------- = (eq. 23) v outripple i l esr ? ? = (eq. 24) c outtran i out 2 l ? v out 2 v outmax vout ----------------------- - ?? ?? 2 1 C ?? ?? ? --------------------------------------------------------------- ----- - = (eq. 25)
ISL78268 fn8657 rev 3.00 page 29 of 34 december 12, 2014 ceramic capacitors must be used at the vin pin of the ic and multiple ceramic capacitors including 1f and 0.1f are recommended. place these capacitors as close as possible to the ic. power mosfet the external mosfets that are driven by the ISL78268 controller need to be carefully selected to optimize the design of the synchronous buck regulator. since the ISL78268 input voltage can be up to 55v, the mosfet's bvdss rating needs to have enough voltage margin against input voltage tolerance and ph node voltage transient during switching. as the ug and lg gate drivers are 5v output, the mosfet vgs need to be in this range. the mosfet should have low total gate charge (q gd ), low on-resistance (r ds(on) ) at vgs = 4.5v (less than 10m is recommended) and small gate resistance (r g <1.5 is recommended). it is recommended that the minimum vgs threshold should be higher than 1.2v but not exceeding 2.5v. this is because of the consider ation of large gate pull-down current associated by gate-drain current at low side transistor due to the high speed transition of phase node and limitation of maximum gate drive voltage, which is 5.2v (typ) for low-side mosfet and lower than 4.5v (typ) due to diode drop of boot diode for high-side mosfet. bootstrap capacitor the power required for high-side mosfet drive is provided by the boot capacitor connected between boot and ph pins. the bootstrap capacitor can be chosen using equation 26 : where q gate is the total gate charge of the high-side mosfet and dv boot is the maximum droop voltage across the bootstrap capacitor while turning on the high-side mosfet. though the maximum charging voltage across the bootstrap capacitor is pvcc minus the bootstrap diode drop (~4.5v), large excursions below gnd by ph node requires at least 10v rating for this ceramic capacitor. to keep enough capacitance over the biased voltage and temperature ra nge, a good quality capacitor such as x7r or x5r is recommended. resistor on bootstrap circuit in the actual application, someti mes a large ringing noise at the ph node and the boot node are observed. this noise is caused by energy stored in the body diode of the low-side mosfet when it is turning off, parasitic ph node capacitance due to pcb routing, and the parasitic inductance. to reduce this noise, a resistor can be added between the boot pin and the bootstrap capacitor. a large resistor value will reduce the ringing noise at ph node but limits the charging of the bootstrap capacitor during the low-side mosfet on-time, especially when the controller is operating at very high duty cycle. typically, up to 10 resistor is used for this purpose. loop compensation design the ISL78268 uses constant fr equency peak current mode control architecture with a gm amp as the error amplifier. an external current sense resistor is required for the peak current sensing and overcurrent protection. figures 49 and 50 show the conceptual schematics and control block diagram, respectively. the output stage consists of a power stage (g v (s)) which converts the duty signal to output voltage and internal current loop stage which converts duty to sense current. power stage transfer functions transfer function at power stage (g v (s)) can be expressed as equation 27 . where, c boot q gate dv boot -------------------- ? (eq. 26) figure 49. conceptual block diagram of peak current mode controlled buck regulator figure 50. conceptual control block diagram g v s ?? vin 1 s ? esr ----------- - + ?? ?? 1 1 s q p ? n ? ------------------ s ? n ------ - ?? ?? 2 ++ -------------------------------------------------- - ?? = (eq. 27) ? esr 1 c out r esr ? ----------------------------- = ------------- ? ? ? n 1 lc out ? ------------------------ - =
ISL78268 fn8657 rev 3.00 page 30 of 34 december 12, 2014 internal current loop transfer functions transfer function from control to inductor current (g i (s)) is given by equation 28 . where, pwm comparator gain fm the pwm comparator gain fm for peak current mode control is given by equation 29 . where m sl is the slew rate of the slope compensation and m a is the inductor current slew rate while high-side mosfet is on and given as equation 30 . where r s is the gain of the current sense amplifier. total transfer function from pwm comparator to power stage the total transfer function from pwm to power stage including internal current sense loop is expressed as equation 31 (assuming f m *g i (s)*r s >>1). equation 31 shows that the system is a single order system. therefore, a simple type-2 compensator can be used to stabilize the system. in the actual application, however, an extra phase margin will be provided by a type-3 compensator. compensator design the transfer function at error amplifier and its compensation network will be expressed as equation 32 . if r oea >>r cmp , c cmp1 >>c cmp2 , and r oea = infinite, the equation can be simplified as shown in equation 33 : where, g i s ?? vin r out ------------- 1 s ? o ------ - + ?? ?? 1 1 s q p ? n ? ------------------- - s ? n ------ - ?? ?? 2 ++ ---------------------------------------------------- - ?? = (eq. 28) ? o 1 c out r out ? ------------------------------- = ------------- ? ? ? n 1 lc out ? ------------------------ - = ---------------- 1 m a m sl + ?? t ? ------------------------------------- - == (eq. 29) m a r s vin v out C l ---------------------------- - ? = (eq. 30 figure 51. converted sense current waveform m sl m b m sl +m a slope compensation adder v ramp t t on t off total v ramp v c converted h/s inductor current m a ?? f m 1f m g i s ?? r s ?? + ---------------------------------------------- g v s ?? r out r s ----------- - 1 s ? esr ----------- - + 1 s ? o ------ - + --------------------- - ? ?? ?? ?? ?? ?? ?? ? ? = (eq. 31) figure 52. type-3 compensator - + gm vref vo r cmp1 c cmp2 fb comp r fb1 r fb0 r 1 c 1 c cmp1 r oea he2 he1 ?? v comp v fb ----------------- g m z comp = ? == (eq. 32) g m 1sr cmp c cmp1 + ?? r oea 1sr cmp c cmp1 r eoa c cmp1 c cmp2 + ?? + ?? c cmc2 c cmp1 r cmp r out s 2 ++ --------------------------------------------------------------- --------------------------------------------------------------- --------------------------------------------------------------- ----------------------------- ?? g m 1sr cmp c cmp1 ?? + sc cmp1 1sr cmp c cmp2 ?? + ?? ?? --------------------------------------------------------------- -------------------------- - ? ? 1 s ------ - 1 s ? z2 --------- - + 1 s ? p2 ---------- + -------------------- ? == (eq. 33) ? 1 g m c cmp1 ----------------- - = ? z2 1 r cmp c cmp1 ? ------------------------------------- - = ? p2 1 r cmp c cmp2 ? ------------------------------------- - =
ISL78268 fn8657 rev 3.00 page 31 of 34 december 12, 2014 the transfer function at the feedback resistor network is: where, the total transfer function with compensation network and gain stage will be expressed; from equation 36 , desired pole and zero locations can be determined as in equations 37 through 42 . in general, set f z2 and f z1 close to the f po . set f p2 near the desired bandwidth. set f p1 close to f zesr . vcc input filter to provide a quiet power rail to the internal analog circuitry, it is recommended to place rc filter between pvcc and vcc. a 10 resistor between pvcc and vc c and at least 1f ceramic capacitor from vcc to gnd are recommended. current sense circuit to set the current sense resistor , the voltage across the current sense resistor should be limited to less than 0.3v. in a typical application, it is recommended to set the voltage across the current sense resistor between 30mv to 100mv for the typical load current condition. layout consideration for dc/dc converter design, the pcb layout is a very important to ensure the desired performance. 1. place the input ceramic capacitor as close as possible to the vin pin and power ground connecting to the power mosfet. keep this loop (input ceramic capacitor, ic vin pin and mosfet) as small as possible to reduce voltage spikes induced by the trace parasitics. 2. place the input aluminum capacitor close to ic vin and ceramic capacitors. 3. keep the phase node copper area small but large enough to handle the load current. 4. place the output ceramic and aluminum capacitors as close as possible to the power stage components. 5. place multiple vias under the thermal pad of the ic. the thermal pad should be connected to the ground copper plane with as large an area as possible in multiple layers to effectively reduce the thermal impedance. 6. place the 4.7f decoupling ceramic capacitor at the vcc pin and as close as possible to the ic. put multiple vias close to the ground pad of this capacitor. 7. keep the bootstrap capacitor as close as possible to the ic. 8. keep the driver traces as short as possible and try to avoid using a via in the driver path to achieve the lowest impedance. 9. place the current sense resistor as close as possible to the ic. keep the traces of current sense lines symmetric to each other to avoid undesired switching noise injections. h e1 s ?? r fb0 r fb0 r fb1 + --------------------------------- - 1 s ? z1 --------- - + 1 s ? p1 ---------- + -------------------- ? = (eq. 34) ? z1 1 c 1 r fb1 r 1 + ?? ? ------------------------------------------ - = ? p1 1 c 1 r fb1 r fb0 ? r fb1 r 1 ? r fb0 r 1 ? ++ r fb1 r fb0 + --------------------------------------------------------------- -------------------------------- ? --------------------------------------------------------------- ------------------------------------------- - = ?? g t s ?? h e1 s ?? h e2 s ?? ?? = (eq. 35) g open s ?? r o r s ------ 1 s ? esr ----------- - + 1 s ? o ------ - + --------------------- - ? ?? ?? ?? ?? ?? ?? r fb0 r fbo r fb1 + --------------------------------- - 1 s ? z1 --------- - + 1 s ? p1 ---------- + -------------------- ? ?? ?? ?? ?? ?? ?? ? 1 s ------- 1 s ? z2 --------- - + 1 s ? p2 ---------- + -------------------- ? ?? ?? ?? ?? ?? ?? ?? = (eq. 36) f po ? o 2 ? ? ---------- - 1 2 ? c out r out ?? ? ----------------------------------------------- == (eq. 37) f z1 ? z1 2 ? ? ---------- - 1 2 ? c 1 r fb1 r 1 + ?? ?? ? ---------------------------------------------------------- - == (eq. 38) f z2 ? z2 2 ? ? ---------- - 1 2 ? c cmc1 r cmp ?? ? ---------------------------------------------------- - == (eq. 39) f p1 ? p1 2 ? ? ---------- - r fb1 r fb2 + 2 ? c 1 r fb1 r fb0 ? r fb1 r 1 ? r fb0 r 1 ? ++ ?? --------------------------------------------------------------- ---------------------------------------------------- == (eq. 40) f p2 ? p2 2 ? ? ---------- - 1 2 ? c cmp2 r cmp ?? ? ----------------------------------------------------- - == (eq. 41) f zesr ? esr 2 ? ? ----------- - 1 2 ? c out r esr ?? ? --------------------------------------------- == (eq. 42)
ISL78268 fn8657 rev 3.00 page 32 of 34 december 12, 2014 revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change december 12, 2014 fn8657.3 fu nctional pin description page 3, fsync description. changed from: th ere is a 100ns delay from the fsync pin's?. to: there is a 325ns dela y from the fsync pin's?. page 4, pvcc description. changed from: the pvcc operating range is 4v to 5.4v. to: the pvcc operating range is 4.75v to 5.5v. vcc description. changed from: range of 4.7v to 5.5v, to: range of 4.75v to 5.5v, typical application schematics page 7, left side changed from: hic/latch:connect to either vcc for latch-off mode or gnd for hiccup mode to: hic/latch:connect to either vcc fo r hiccup mode or gnd for latch-off mode page 8, left side changed from: hic/latch:connect to either vcc for latch-off mode or gnd for hiccup mode to: hic/latch:connect to either vcc fo r hiccup mode or gnd for latch-off mode page 9, left side changed from: hic/latch:connect to either vcc for latch-off mode or gnd for hiccup mode to: hic/latch: connect to either vcc for hiccup mode or gnd for latch-off mode page 10, electrical specification table, test condition of input voltage range, changed from "for vin = 5 the internal ... " to "for vin = 5v, the internal ..." elecrical spec table, page 11 , phase lock loop locking time changed in test conditions: cpllcmp2=_nf to: cpllcmp2=1nf page 20, operation description, 2nd sentence changed from: "such as input and output overvoltage protection, output overvoltage protection" to: "input overvoltage protection, output overvoltage protection" page 22, synchronization with external clock, 2nd paragaph changed from : the delay time of ug rising from the external clock rising edge is 100ns (typ). to: the delay time of ug rising from the external clock rising edge is 325ns (typ). page 25, figure 46 changed: "ma1 = ma + msl" to: "ma1 = ma + msl" page 30, eq. 30 changed : mn=rs*?? to: ma=rs*?? figure 51 changed: mb to: ma august 1, 2014 fn8657.2 on page 1 in the features section, updated the 5th bullet from ?low shutdown current, iq<3a? to ?low shutdown current, iq<1a?. in the ?block diagram? on page 6, reversed the ?+? and ?-? gm_amp input polarity. july 22, 2014 fn8657.1 added related literature section on page 1 and ISL78268eval1z information to the ordering information table on page 5 june 18, 2014 fn8657.0 initial release.
fn8657 rev 3.00 page 33 of 34 december 12, 2014 ISL78268 intersil automotive qualified products are manufactured, asse mbled and tested utilizing ts16949 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2014. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support
ISL78268 fn8657 rev 3.00 page 34 of 34 december 12, 2014 package outline drawing l24.4x4h 24 lead quad flat no-lead plastic package rev 0, 09/11 c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 4.00 a b 4.00 (4x) 0.15 6 pin 1 index area 19 pin #1 index area 24 2.50 20x 0.50 exp. dap 6 1 18 12 24x 0.40 0.10 7 6 2.50 see detail "x" seating plane 0.08 0.10 c c c ( 3.80 ) ( 2.50 ) ( 24 x 0.60) (24x .25) ( 20x 0.50) ( 3.80 ) ( 2.50) typical recommended land pattern 0.10 24x 0.25 +0.07 a m c 4 2.50 0.05 sq. 0.25 min (4 sides) -0.05 0.90 0.10 dimensioning and tolerancing conform to amsey14.5m-1994. dimension applies to the metallized terminal and is measured the configuration of the pin #1 identifier is optional, but mus t be dimensions in ( ) for reference only. between 0.15mm and 0.30mm from the terminal tip. tiebar shown (if present) is a non-functional feature. unless otherwise specified, tolerance : decimal 0.05 4. 5. 6. 3. 2. dimensions are in millimeters. notes: 1. located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 13 compliant to jedec mo-220 vggd-8 7. b bottom view detail "x" side view top view

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